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5.15 Switching Characteristics—Digital Audio Output (DAO) Port
5.15 Switching Characteristics—Digital Audio Output (DAO) Port
DAO_MCLK period
DAO_MCLK duty cycle
Parameter
Symbol
T daomclk
—
Min
40
45
Max
—
55
Unit
ns
%
DAO_SCLK period for Master or Slave
mode 1
T daosclk
40
—
ns
DAO_SCLK duty cycle for Master or Slave mode 1
—
40
60
%
1.Master mode timing specifications are characterized, not production tested.
Table 5-1. Master Mode (Output A1 Mode) 1 , 2
Parameter
DAO_SCLK delay from DAO_MCLK rising edge, DAO_MCLK as an input
DAO_LRCLK delay from DAO_SCLK transition, respectively 3
DAO_SCLK delay from DAO_LRCLK transition, respectively 3
DAO1_DATA[3:0], DAO2_DATA[1:0] delay from DAO_SCLK transition 3
Symbol
t daomsck
t daomstlr
t daomlrts
t daomdv
Min
—
—
—
—
Max
19
8
8
10
Unit
ns
ns
ns
ns
1.Master mode timing specifications are characterized, not production tested.
2.Master mode is defined as the CS48xx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce DAO_SCLK, DAO_
LRCLK.
3.This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the point at which the data is valid.
t daomclk
DAO_MCLK
t daomsck
DAO_SCLK
DAOn_DATAn
t daomstlr
DAO_LRCLK
16
Note:
In these diagrams, Falling edge is the inactive edge of DAO_SCLK.
Figure 5-9. Digital Audio Output Port Timing, Master Mode
DS734F5
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